As is known, when reading a nonvolatile memory cell, the logic state (either erased or written) of the memory cell should be discriminated as fast as possible.
For this purpose, the cell to be read is connected to a read circuit, an embodiment whereof is shown in FIG. 1. In detail, a memory cell 1 belonging to a memory array 2 has its drain terminal connected to a bit line 11, connected, via a decoding and biasing circuit 3, to a read circuit 4 comprising a current-to-voltage converter 5, an equalization circuit 6, and a comparator 7. The memory cell 1 to be read moreover has its source terminal connected to ground and its gate terminal connected to a word line 8 biased at a voltage V.sub.B.
A reference cell 10 has its source terminal grounded, its gate terminal biased at a voltage V.sub.G, and its drain terminal connected to a reference line 12, which is also connected to the current-to-voltage converter 5 through the decoding and biasing circuit 3.
The decoding and biasing circuit 3, of a known type, has the purpose of selecting the bit line 11 connected to the drain terminal of the memory cell 1 to be read. In addition, the decoding and biasing circuit 3 has the purpose of appropriately biasing the bit line 11, as well as the reference line 12.
The read circuit 4 detects the current I.sub.M and I.sub.R flowing, respectively, in the memory cell 1 to be read and in the reference cell 10, and compares them to establish whether the memory cell 1 is written or erased. In particular, comparison between the currents I.sub.M and I.sub.R is made by evaluating the unbalancing of the array node 14 and reference node 15, which form outputs of the current-to-voltage converter 5 and are connected, through the decoding and biasing circuit 3, respectively to the bit line 11 and to the reference line 12.
The equalization circuit 6 comprises pre-charging and equalization circuits that are essential for obtaining reduced times of access to the memory cell 1 to be read. The equalization circuit 6 has the purpose of initially bringing the array node 14 and the reference node 15 (on which voltages V.sub.M and V.sub.R are present) to the same voltage value, so that, when they are released, they may reach the final values quickly and without any indecision. An example of timing of the equalization circuit 6 is shown in FIG. 2, in which ATD is an address transition signal having a pulse at the transition of the addresses; SAEQ is an equalization control signal; V.sub.M and V.sub.R are the voltages at the array node 14 and reference node 15, respectively; and V.sub.B is the row voltage applied to the word line 8 to which the memory cell 1 to be read is connected.
In FIG. 2, following upon transition of an address, the address transition signal ATD presents a pulse, which, in turn, activates the equalization phase, determining the equalization control signal SAEQ to switch from low to high. Switching of the equalization control signal activates the equalization circuit 6, and the voltages V.sub.M and V.sub.R on the array node 14 and the reference node 15, respectively, are equalized (portion EQ), and hence have the same value. In the meantime, the row voltage V.sub.B increases up to the supply voltage V.sub.dd and is then boosted via a charge pump circuit (not shown--FIG. 1), as is usual in memories operating at a low supply voltage. As soon as the equalization control signal SAEQ switches back to low again, the array node 14 and the reference node 15 are free to move according to the intensity of the currents in the memory cell 1 and in the reference cell 10. In the example of FIG. 2, the memory cell 1 to be read is erased; consequently, the voltage VM on the array node 14 decreases with respect to the equalization value, while the reference voltage V.sub.R on the reference node 15, after a short transient, increases with respect to the equalization value.
The duration of the pulse of the equalization control signal SAEQ must be selected with great care since it depends upon the evolution of the voltages V.sub.M and V.sub.R on the array node 14 and the reference node 15, and thus the access time to the memory cell 1 to be read. In particular, to have fast reading without uncertainties, the equalization circuit must be deactivated only when the erased array cells 1 absorb a current greater than that of the reference cell 10. In particular, with a longer duration, reading becomes unacceptably slow, and with a shorter duration, it is possible that there will be uncertainty of reading or else it is necessary for the read time to be decidedly lengthened. In fact, if the voltage on the gate terminal of the memory cell 1 to be read has not yet reached the optimal value, the erased cells could be interpreted momentarily as being written and the voltages on the array node 14 and the reference node 15 could move in the direction opposite to the correct one. In this case, only when the current in the addressed bit line 11 exceeds the current of the reference line 12, do the voltages on the array node 14 and the reference node 15 invert their direction; from this moment on, a certain time is in any case necessary for the voltages on the array node 14 and the reference node 15 to cross and move on to the correct values, thus leading all round to a considerable loss of time.
In the known circuits, to determine the duration of the pulse of the equalization control signal SAEQ the voltage supplied to the drivers of the word lines 8 is observed; only when this (boosted) voltage exceeds by a predetermined amount the supply voltage V.sub.dd (voltage V.sub.EE in FIG. 2), an appropriate sensing circuit blocks equalization, causing the equalization control signal SAEQ to switch. An example of a circuit for generating the equalization control signal SAEQ is shown, for example, in FIG. 3.
In detail, FIG. 3 shows a charge pump stage 18 of the "single-shot" type based, in a per se known manner, upon the alternation between a charging phase and a charge transfer phase, controlled by the switching of an enabling signal AN. In particular, during the charging phase (enabling signal AN high) a capacitor 19 is charged at the supply voltage V.sub.dd. During the charge transfer phase (enabling signal AN low) the capacitor 19, the bottom terminal of which is raised to the supply voltage V.sub.dd, transfers its charge to an output capacitor 21.
In this way, the voltage on the output capacitor 21, referred to as monitored voltage V.sub.1, and supplied to the driver 22 of the addressed word line 8, is raised to theoretically almost twice the supply voltage V.sub.dd. The monitored voltage V.sub.1 is supplied to a comparator 25 which compares it with a predetermined threshold voltage V.sub.2, for example equal to the supply voltage V.sub.dd plus a quantity equal to the threshold voltage V.sub.th of a P-channel transistor (V.sub.2 =V.sub.dd +V.sub.th); as soon as the comparator 25 switches, an equalization signal generating stage, here represented by a flip-flop 27, is reset, as activated by the address transition signal ATD.
In the latest generations of nonvolatile memories, there has been a reduction of the supply voltage V.sub.dd (which has required cell gate voltage boosting), and an increase in the size of the memory array. This latter fact has determined an increase in the time constant associated both to the bit lines and to the word lines.
In particular, the word lines may now have time constants of the order of some ten nanoseconds, which it is to be taken into account when defining the duration of the equalization interval. In fact, the erased cells connected to the end of the word line are delayed in conducting the current necessary for correct reading, as compared to the erased cells connected to the start of the word line.
With the known circuit of FIG. 3, which observes the voltage at the output of the charge pump stage 18 or at the input to the word line 8, it is not possible to foresee in any way the value of the voltage on the gate terminal of the last cell connected to the word line. On the other hand, the progress of the voltage on the last cell may be considerably delayed with respect to the first cell, as shown in the plot of FIG. 4, where the voltage V.sub.B1 represents the gate voltage of the first cell of the addressed word line, and the voltage V.sub.B2 represents the gate voltage of the last cell of the addressed word line.
As may be noted, to guarantee reading also of the last cell, preventing dangerous oscillations of the reference node 15, it is necessary to delay the end of equalization by a time interval equal to .DELTA.. However, given that the resistance of the word lines may have a dispersion of between 50% and 100%, and hence the time interval .DELTA. may vary from memory to memory, a fixed delay does not eliminate the problem discussed above.